This application claims priority under 35 USC § 119 to Korean Patent Application No. 2004-60763, filed on Aug. 2, 2004, the contents of which are incorporated herein by reference in their entirety for all purposes.
1. Field of the Invention
The present invention relates generally to charge pumps, and more particularly to a charge pump having up and down currents that are balanced and constant for reducing jitter in a phase-locked loop.
2. Description of the Related Art
A phase-locked loop (PLL) is widely used for various applications such as a clock recovery circuit in a communication system or a frequency synthesizer for synthesizing a higher frequency using a lower frequency. In general, the phase-locked loop includes a phase frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO).
FIG. 1 is a block diagram illustrating a conventional phase-locked loop. Referring to FIG. 1, a phase frequency detector 110 generates an up signal UP and a down signal DN based on a phase (or frequency) difference between a reference signal Vi and a feedback signal Vo. A charge pump 120 draws an up current lUP through a loop filter 130 when the up signal UP is activated or draws a down current lDN from the loop filter 130 when the down signal DN is activated. The loop filter 130 is charged or discharged in response to the up/down currents lUP/lDN to generate a loop filter voltage.
A voltage-controlled oscillator 140 generates the feedback signal Vo based on the loop filter voltage. In this manner, the up signal UP and the down signal DN are generated such that a phase (or frequency) difference between the reference signal Vi and the feedback signal Vo is reduced.
FIGS. 2A and 2B illustrate operation of the charge pump 120 in response to the up signal and the down signal. Referring to FIG. 2A, an up switch 230a is closed when the up signal UP is activated such that the up current lUP is supplied from an up current source 210a to charge a loop filter 250a. Referring to FIG. 2B, a down switch 240b is closed when the down signal DN is activated such that the down current lDN is drawn by a down current source 210b to discharge a loop filter 250b. The loop filters 250a and 250b, charged or discharged, generate a control signal Vctrl provided to the VCO 140.
An important performance aspect of the phase-locked loop depends on a performance of the charge pump. Particularly, the charge pump is desired to operate over a wide voltage range with balanced up and down currents lUP and lDN. When the up current IUP is not substantially matched with the down current IDN, a ripple may be continuously generated when the phase-locked loop is locked. Moreover, jitter may be disadvantageously increased due to degradation of tracking characteristics.
FIG. 3 is a circuit diagram illustrating a conventional charge pump. Referring to FIG. 3, the conventional charge pump includes a reference current source Iref, PMOS (P-channel metal oxide semiconductor) transistors MP1 and MP2, NMOS (N-channel metal oxide semiconductor) transistors MN1, MN2 and MN3, and up/down switches UP and DN. The NMOS transistor MN1 and the PMOS transistor MP1 form a current mirror with the NMOS transistor MN2 and the PMOS transistor MP2, respectively, to produce the up current IUP proportional to a current drawn from the reference current source Iref. The NMOS transistor MN3, forming a current mirror with the NMOS transistor MN1, produces the down current IDN proportional to the current drawn from the reference current source Iref.
The up switch UP is closed when the up signal UP is activated such that the up current IUP flows to an output terminal OUT of the charge pump. Alternatively, the down switch DN is closed when the d own signal DN is activated to d raw the down current IDN from the output terminal OUT. One of the up signal and down signal UP and DN is activated.
The up and down currents IUP and IDN are desired to be the same, and such currents are both generated by mirroring the reference current Iref. However, as a voltage at the output terminal OUT varies in a range from about OV to about VDD, the up and down currents IUP and IDN become different from each other because the PMOS and NMOS transistors MP2 and MN3 have finite resistance.
That is, the PMOS and NMOS transistors MP2 and MN3 operate in a saturation region where a drain current Ids of each of such transistors varies with the drain-to-source voltage Vds as follows:
                              Ids          =                                    1              2                        ⁢            μ            ⁢                                                  ⁢            Cox            ⁢                                                  ⁢                          W              L                        ⁢                                          (                                  Vgs                  -                  Vth                                )                            2                        ⁢                          (                              1                +                                  λ                  ⁢                                                                          ⁢                  Vds                                            )                                      ,                            [                  Expression          ⁢                                          ⁢          1                ]            wherein μ is a mobility of a charge carrier in a channel, Cox is a capacitance per unit area formed by a gate electrode and the channel, W is a width of the channel, L is a length of the channel, Vgs is a gate-to-source voltage, Vth is a threshold voltage of the transistor, and λ is a channel length modulation coefficient.
Thus, the drain current Ids increases as the drain-to-source voltage Vds increases, and the drain current Ids decreases as the drain-to-source voltage Vds decreases, for the NMOS transistor. On the other hand, the drain current Ids increases as the source-to-drain voltage Vsd increases, and the drain current Ids decreases as the source-to-drain voltage Vsd decreases, for the PMOS transistor.
Therefore, when the voltage at the output terminal OUT of the charge pump in FIG. 3 is increased, the source-to-drain voltage Vsd of the PMOS transistor MP2 is decreased, thereby decreasing the up current IUP. Also, the drain-to-source voltage Vds of the NMOS transistor MN3 is increased, thereby increasing the down current IDN. Conversely, when the voltage at the output terminal OUT is decreased, the source-to-drain voltage Vsd of the PMOS transistor MP2 is increased, thereby increasing the up current IUP. Also, the drain-to-source voltage Vds of the NMOS transistor MN3 is decreased, thereby decreasing the down current IDN. Thus, the up current IUP and the down current IDN may not be precisely matched from the variation of the voltage at the output terminal OUT.
FIG. 4 is a plot illustrating simulation results for the up current IUP and the down current IDN according to the voltage VOUT at the output terminal of the charge pump in FIG. 3. Referring to FIG. 4, as the output voltage VOUT increases, the up current IUP decreases while the down current IDN increases resulting in a current mismatch which in turn may result in jitter of the phase-locked loop.
A phase locked loop charge pump circuit as disclosed in U.S. Pat. No. 6,107,889 includes a reference current loop for generating a reference current proportional to a reference voltage and a replication feedback loop for replicating a loop filter voltage at a coupling node to provide the reference current as an up current. According to U.S. Pat. No. 6,107,889, the up current is replicated from the down current so that the up current may be substantially identical to the down current.
However, the charge pump circuit disclosed in U.S. Pat. No. 6,107,889 changes the up current according to the change of the down current for enhanced current matching. However, such up and down currents still have variance. For example, when the down current is changed by ΔI, the up current is also changed by ΔI from matching with the down current. Such current variance may lower the operating speed of the phase-locked loop and may affect frequency characteristics of the phase-locked loop to degrade the performance of the phase-locked loop. Therefore, a charge pump that generates the up/down currents that are balanced at a constant current level is desired.